The present invention relates in general to a method for fabricating a transistor, more particularly to improvements in operation ability and switching time, along with a method for the fabrication of transistor having a lightly doped drain structure (hereinafter "LDD").
As the integration degree of semiconductor device is high, the size of the semiconductor device becomes miniaturized smaller and smaller in the submicron region. In order to satisfy the scale-down, new silicon fabrication technologies have been developed and advanced.
A method for fabricating a submicron semiconductor device is required to keep the device performance high as well as to secure the device reliability, keeping on scaling down the semiconductor device.
In particular, as this miniaturization proceeds toward higher integration density, physical limits are generated. For example, the degradation caused by hot carriers, a problem relating to the device reliability, has been one of the most serious problems.
In an effort to overcome this problem, there has been suggested a method for controlling the charge entrapped in an oxide film on an n.sup.- region which is a low density impurity region of the source and drain region having an LDD structure. In the above view point, an inverse-T type LDD (hereinafter "ITLDD") structure is disclosed in U.S. Pat. Nos. 4,907,048 and 4,963,054.
Hereinafter, the inverse-T gate structure is to be described along with the problems included therein for better understanding of the background of the present invention.
Referring initially to FIG. 1, there is illustrated process steps in the fabrication of an ITLDD transistor device proposed in aforementioned patents.
First, a photoresist pattern PR is deposited upon an oxide film 13 covering a polysilicon layer 12 which overlays a gate oxide film atop a p type semiconductor substrate as shown in FIG. 1A.
Subsequently, using the photoresist pattern as a mask, the oxide film 13 is removed and the polysilicon layer 12 is partially removed so as to leave a central trunk 12'. The polysilicon layer 12 is thinned to leave a layer of thin thickness, followed by the removal of the photoresist pattern PR, as shown in FIG. 1B.
FIG. 1C shows the process to implant an n type impurity at a low density through the thinned layer to form lightly doped n.sup.- regions 14 and 15.
Next, sidewall spacers 16 are formed at the both sides of the central trunk 12' by depositing an oxide film on the resulting structure and etching back it, as shown FIG. 1D.
As illustrated in FIG. 1E, the thinned layer of polysilicon which was formed when a gate was formed is then removed by means of an etch process which utilizes the spacers 16 as masks, leaving an inverse-T gate structure.
Finally, an n type impurity is implanted, as indicated by arrows, at a high density to form n.sup.+ regions 17 and 18 within the formed n.sup.- regions 14 and 15, the sidewall spacers 16 serving as masks to offset an n type impurity of high density. As a result, there is formed the source 14, 17 and drain 15, 18 of LDD structure.
In such ITLDD transistor device, since the n.sup.- regions 14 and 15 are formed in such a way to completely overlap with the gate to have influence on themselves, the immunity against hot carriers can be improved and thus, the device degradation caused by the hot carriers can be prevented.
However, this fabrication process includes a problem as indicated below. Following the formation of the polysilicon layer for gate, as introduced above, the polysilicon layer is subjected to an etch process to form an inverse-T shape with the gate mask. At this time, instead of removing the entire layer, it is etched so as to be left thin. Care must be taken so as not to overthin the conductive layer. In other words, it is very difficult to control the etch stop endpoint.
Referring now to FIG. 2, there is shown another inverse-T gate transistor device. This structure is to solve the problem of the etch stop endpoint which appears in fabricating an ITLDD gate transistor device of FIG. 1 and is disclosed in U.S. Pat. No. 5,082,794.
The inverse-T gate transistor device proposed in the just mentioned patent is formed of a p type semiconductor substrate 11 which is sectioned by field oxide films 12 into an active region 14 and an device separation region. The active region of the semiconductor substrate 20 is covered with an oxide film 16, followed by the formation of first polysilicon layer 17 over the resulting structure, as shown in FIG. 2A.
Upon the first polysilicon layer 17 is entirely deposited an oxide film 18 which is then subjected to an etch process by use of a mask (not shown) to provide a gate region, as shown in FIG. 2B. A p type impurity is ion-implanted, as indicated by arrow of FIG. 2B, to form a p type region 25 which plays a role in controlling a threshold voltage.
A second polysilicon 26 is buried in the etched portion of the oxide film by a selective chemical vapor deposition process, as shown in FIG. 2C.
The oxide film 18 is removed and then, using the second polysilicon layer 26 as a mask, an n type impurity is ion-implanted at a low density to form LDD regions 27 of n.sup.- region, as shown in FIG. 2D.
Next, a pair of oxide film spacers 31 are formed at both sides of the second polysilicon layer 25, followed by the formation of a high density n.sup.+ source 33 and a high density n.sup.+ drain region 34 by ion implantation of an n type impurity at a high density, as shown in FIG. 2E.
Using the second polysilicon layer 26 and the oxide film spacer 31 as a mask, the first polysilicon layer 26 is subjected to an etch process to form an ITLDD gate transistor, consequently.
The fabrication process illustrated in FIG. 2 is precise in fabricating an inverse-T gate as compared with that illustrated in FIG. 1. However, the ITLDD gate transistor is thicker than the transistor of FIG. 1 and thus, the device flatness, that is, the topography thereof becomes deteriorated.
In fabricating the ITLDD gate transistor, when an ion implantation process is carried out in order to form the source region and the drain region, a channeling phenomenon (the electric characteristics of transistor are changed by the result that ion dopants implanted penetrate into a gate, following after the polysilicon grains constituting the gate) may be generated. In addition, since the gate is formed by the selective chemical vapor deposition, the side surfaces of the gate may be not clear.